1. Field of the Invention
The present invention generally relates to the art of integrated circuits, and more particularly, to a circuit and method for configuring a memory device.
2. Description of the Relevant Art
Typical ISA bus systems contain several cards, each one of which receives broadcast CPU access requests. Each card, however, differentiates among the access requests to identify those it should respond to. This is facilitated by each card, for example, knowing what ISA memory space is allocated to it. Prior to ISA Plug and Play protocol, a standard well known in the industry, ISA resources, e.g., ISA memory space, were allocated to the connected cards by the system user. To this end, analysis was required to determine the amount of memory space available in the ISA system, how much memory is required by, for example, a newly coupled card, and setting the new card to utilize a range of available memory space.
ISA Plug and Play was implemented to allow the operating system to configure the cards. In general, the operating system identifies the ISA cards connected thereto, queries each card to determine the resources including the amount of memory space it needs, and allocates the available ISA resources accordingly. The CPU initiates its sequence by isolating each card one at a time. Each ISA card has a unique identifier defined by a code, portions of which are indicative of card manufacturer, card model, and card serial number. As can be seen, no two cards can have the same identifier since each card model manufactured by a company will have a different serial number. During isolation, all the card IDs are accessed to determine which has the lowest serial number. The isolated card is queried for its ISA resource requirements, i.e., its configuration information. The card with the lowest serial number is directed to receive the immediate configuration instructions from the CPU. The other cards, will ignore the immediate configuration commands. Once one of the cards is isolated and configured, the operating system identifies the next card with the lowest serial identification and queries the configuration information stored therein, which is subsequently used by the CPU to allocate ISA resources accordingly.
The card identifier and the configuration information are typically stored in a serial read only memory (ROM) within each card. Serial ROMs are the preferred device to store the configuration information since they are capable of being programmed with individual identification codes along with common configuration information. Further, serial ROMs can be programmed after the individual cards are assembled.
The 93x6 family of serial ROMs is a popular, low-cost ROM for storing such configuration information. Different versions of the 93x6 ROM contain differing amounts of memory. Moreover, the 93x6 ROMs have similar but not identical protocols for accessing information stored therein.
Shown in FIG. 1 is a typical 93x6 ROM 10 generally available on the market. The ROM includes a memory array 12 in data communication with data register 14, mode decode logic circuit 16, internal clock and generation circuit 20, address decoder 22, address counter 24, and output buffer 26. Data register 14 stores data to be written to or read from memory array 12 at an address specified in address decoder 22.
Configuration data is read from the ROM 10 using four digital signals: chip select (CS), clock (CLK), data in (DI), and data out (DO). When CS is high, ROM 10 is selected or enabled. A low level on CS deselects or disables ROM 10 and forces it into standby mode. CLK is used to synchronize the communication between a master device and ROM 10. Opcode and address, bits are clocked serially into DI on the positive edge of CLK. Data bytes are clocked out serially from DO on the positive edge of CLK, one bit at a time in response to the ROM 10 receiving the read instruction and address.
ROM 10 ignores CLK if CS is low. If CS is high, but a start condition has not been detected, any number of clock signals can be received by ROM 10 without changing its status. After detection of a start condition, a specified number of clock signals (respectively low to high transitions of CLK) must be provided to access ROM 10 as will be more fully described below. In a read operation these clock cycles are required to clock in the read instruction and the address to be read, one bit at a time.
DI is used to clock in a start bit, read instruction opcode, and address bits synchronously with the CLK input. DO is used in the read mode to output data synchronously with the CLK input. The start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK. Any read instruction following a start condition will be executed if the required amount of opcode and address bits for any particular instruction is clocked in. After the read instruction is executed, CLK and DI are ignored until a new start condition is detected.
The read instruction outputs serial data of the addressed memory location at DO. A dummy zero bit precedes each word read from the addressed memory. Output data bits will toggle on the rising edge of CLK and are stable after a specified time delay. A sequential read is possible when CS is held high. The memory will automatically cycle to the next register and output sequentially. DO is normally tristated except when reading data from the device.
As noted above, there are several different types of ROMs 10. The main differences between them are in memory size and addressing protocol. ROM 10 implemented as a 9346 type device has 1024 bits (128 bytes) of memory. ROM 10 implemented as a 9356 has 2048 (256 bytes) of memory. The 9356 requires 9 address bits to access a given memory location while the 9346 requires only 7 bits. Since the 9356 and 9346 require a different number of address bits in a read operation, the protocols for accessing the 9356 and 9346 are required to be different.
The required input to DI to read a word from a 9346 type ROM is shown in FIG. 2. Specifically, at time t.sub.1, CS is asserted high and the 9346 tristates DO. Thereafter, the start bit is sent by driving DI high followed by a low to high transition at CLK as seen at time t.sub.2. The read opcode is sent by clocking a high into DI at t.sub.3 followed by a low clocked into DI at t.sub.4. Thereafter, seven address bits are clocked into DI at t.sub.5 -t.sub.12. In response to the last address bit being clocked in, the 9346 drives DO low at t.sub.13. From t.sub.14 -t.sub.22, the 9346 drives one bit of the word selected on DO at each clock edge.
The sequence used for reading a word from the 9356 type of device is similar to that for the 9346 device. However, the 9356 device requires two more address bits to be sequentially clocked into DI. The 9356 ROM like the 9346 ROM drives DO low in response to the last address bit being clocked into DI.
As noted, above, the ISA Plug and Play protocol is an industry standard that allows a personal computer to dynamically allocate system resources to ISA cards. Part of this protocol requires that card configuration data be sent to an ISA bus master. The configuration data is typically stored in the serial ROM described above. The Plug and Play protocol dictates that the configuration data be read from the ROM at certain times.
The configuration information stored in the ROM is typically unique for each ISA card manufactured. Moreover, one card may require more configuration information than other cards. The 9346 and 9356 ROMs can accommodate the differing amount of configuration information required to be stored. It is useful for a single integrated circuit which implements the ISA Plug and Play protocol, to be able to access either the 9346 or 9356 type ROMs to retrieve the configuration information. In other words, the Plug and Play implementing chip should be flexible enough to operate in connection with either the 9346 or 9356 style ROMs. Accordingly, there is a need to develop an integrated circuit that implements the ISA Plug and Play protocol which is able to automatically detect which communication protocol is necessary for accessing an unknown type of serial ROM used to store configuration information.